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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-07-29 13:54:53 +0100 |
|---|---|---|
| committer | Biju Das <biju.das.jz@bp.renesas.com> | 2026-08-05 14:08:17 +0100 |
| commit | a4377c7722b824d3d2eb940eb681cf37b0969a24 (patch) | |
| tree | bb687ebfec8e880750f90ba8d8c440de3fc3defd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 3d33e9c726d677be4087dcb33c1710176e85d9c1 (diff) | |
dt-bindings: display: bridge: renesas,dsi: Document RZ/G3L
The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY
timings and also the PLLCLK is ungateble clock. Add the compatible
string "renesas,r9a08g046-mipi-dsi" to handle these difference for the
Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729125516.230757-2-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions