arm64: dts: qcom: x1e80100: Add deepest idle state

CPU subsystem deepest idle state can lead SoC to low power mode like CxPC
(chip rail power collapse). SoC deepest low power mode requires the PDC
interrupt controller to wake up the SoC as the GIC interrupt controller
is on Cx (chip rail) and will not be functional to wake up the CPU.

PDC monitors both direct SPI interrupts and GPIOs used as interrupts
in SoC low power mode. Further all wake up capable interrupts gets routed
via PDC to GIC when SoC is out of low power mode.

The wake up capable GPIOs used as interrupts were by passing PDC on x1e
with commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup
parent for now") as a result CPU deepest idle state was not added so
far.

The blocker for enabling deepest idle state was GPIO IRQ wakeup support.
The x1e80100 PDC can operate in two modes: pass-through mode (GPIO
IRQs forwarded directly to GIC without latching at PDC) and secondary
controller mode (PDC latches GPIO IRQs and sends them as level IRQs to
GIC).

All the SoCs on Linux so far worked in pass-through mode of PDC.
On some x1e boards the firmware configures the PDC in secondary controller
mode, which caused GPIO interrupt storms as the level latched at PDC gets
never cleared.

The secondary mode is originally a requirement for windows SW platforms
(which could not work with all types of interrupts and require level
interrupts for GPIOs). Initially shipped windows firmware did not have
SCM interface to configure PDC back to pass-through mode if with such
firmware Linux is booted up.

PDC irqchip has got secondary mode and SCM interface support to configure
PDC irqchip mode to pass-through mode on newer firmware where SCM interface
is available and for older firmware on which SCM interface is not present
PDC irqchip works in secondary irqchip mode [1]. Above mentioned commit is
also reverted via [1].

With PDC now working on older firmware as well add the CPU deepest idle
state domain_ss3.

The newly added domain_ss3 state has entry/exit latencies of 2500 us.
The shallower cluster_cl5 state had entry/exit latencies of 2200/4000 us
which are higher than the deeper state. This create an inconsistency that
would confuse the idle governor. Correct cluster_cl5 latencies to 2000 us
each to match production configuration values.

[1] https://lore.kernel.org/linux-arm-msm/20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com/#t

Tested-by: Daniel J Blueman <daniel@quora.org>
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260715-hamoa_pdc_v3-v5-1-00440cfaf711@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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