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| author | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 01:33:30 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 17:20:24 +0530 |
| commit | 834ae6bb795ff85d6c701665a4bb04ca0eeedd5d (patch) | |
| tree | 2998687d6adecdc96373201c6941271aed62839a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 7b1c73d0f7250773536419a7b6982b8faf9ab31b (diff) | |
drm/i915/cmtg: Program VRR control register for CMTG transcoder
Add intel_cmtg_set_vrr_ctl() to program TRANS_VRR_CTL for the
CMTG transcoder. Purposefully avoid using the existing VRR enable
path, as many of its operations are not needed for CMTG.
v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control register along with vrr transcoder
registers. [R-b from Uma]
v4: Split out from vrr timing registers programming.
Bspec: 68989
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-14-animesh.manna@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions