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| author | Ryan Chen <ryan_chen@aspeedtech.com> | 2026-06-24 13:44:59 +0800 |
|---|---|---|
| committer | Brian Masney <bmasney@redhat.com> | 2026-07-28 11:25:30 -0400 |
| commit | 51be18310cd82fc4f1692d9cb7c4f53d26cacd74 (patch) | |
| tree | 23ae6c1264570e01811066646bc477d0d098ef30 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ebd0b73d2137c2277440da04124a0ce7011b2d1a (diff) | |
dt-bindings: clock: ast2700: add PECI clock
Add SCU1_CLK_PECI for the SoC1 PECI controller clock source, and
SCU1_CLK_HPLL_DIV4 which serves as one of the PECI clock mux parents.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions