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| author | Dyllan Kobal <dyllan.kobal@zetier.com> | 2026-06-23 00:58:04 +0000 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-07-15 09:15:43 -0400 |
| commit | db9c882f83d3f3e08069f52d0d2ebf9d131c9ae4 (patch) | |
| tree | 14d0ad192aeee26fbfe19b820159e3ffb89ea0a9 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | b736792e5bd4a62f24e8d1e310bf4a75bfbeaaaa (diff) | |
drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new
dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but
passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second
REG_UPDATE_2 slot.
The current behavior is harmless on DCN3.5 because both fields share the
same bit layout, but it is still incorrect and could break on future
hardware revisions.
Fixes: d36771a03412 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL")
Signed-off-by: Dyllan Kobal <dyllan.kobal@zetier.com>
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions