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| author | Matthew Leung <matthew.leung@oss.qualcomm.com> | 2026-07-07 20:32:48 +0000 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-07-20 16:21:35 +0530 |
| commit | fdfe6417e2e699890f51bcc0b772734a0431e5d2 (patch) | |
| tree | 70b5705061b98dc750ded19783333d3f13471ff2 /tools/perf/scripts/python/bin | |
| parent | 0696cc735dc7ff53297ad2ee649ceed3b1f93d07 (diff) | |
phy: qcom-qmp: Add v10.60 register offsets
Hawi SoC uses v10.60 register definitions for PCIe Gen4 x1. Add the new
register offset headers for all four sub-blocks:
- QSERDES-COM offsets
- QSERDES TX/RX offsets
- PCS offsets
- PCS PCIe-specific offsets
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-3-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions