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authorKathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>2026-07-10 23:16:41 +0530
committerVinod Koul <vkoul@kernel.org>2026-07-22 21:13:32 +0530
commitee6aa0f01d4e8eddf1c7fda49d65c7ef12444e78 (patch)
tree3cd470894aadcf6b5f77b3f53729cab2e40767e5 /tools/perf/scripts/python/bin
parent7218d17e7613d5949cfc6215101493418fa501c0 (diff)
phy: qcom: qmp-pcie: Add IPQ9650 PCIe PHY support
Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe controllers and two Gen3 x1 PCIe controllers. The PHY instances require the on-chip refgen supply. Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with the refgen regulator supply. Note that an on-chip LDO, driven by the SoC CX, supplies the PHY voltages without requiring software control. Note that IPQ9650 does not support CX power collapse or rail scaling. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://patch.msgid.link/20260710-ipq9650_pcie_phy-v3-2-ef6018818d33@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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