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| author | Sean Paul <seanpaul@google.com> | 2026-05-28 19:07:47 -0400 |
|---|---|---|
| committer | Uma Shankar <uma.shankar@intel.com> | 2026-06-02 21:34:41 +0530 |
| commit | de90ca97b21eb60c52e8461e081015434d8bb47f (patch) | |
| tree | 96319c20dac2c4468d191aa4d6d47cce46914e57 /tools/perf/scripts/python/bin | |
| parent | 466a751e17f4cc0c740f6cc8139bae5ba65e8a15 (diff) | |
drm/i915/color: Fix step discontinuity in Pre-CSC Gamma LUT
Clamp Segment 2 to the last user-provided LUT entry value instead of
hardcoding it to 1.0 (1 << 24) to fix a step discontinuity.
Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1
Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-2-sean@poorly.run/ #v2
Changes in v2:
- Split out into separate patches for pre/post csc fixes
- Dropped loop bounds fix in favor of [1]
Changes in v3:
- Fix stale commit message
[1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
Signed-off-by: Sean Paul <seanpaul@google.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260528230817.2455072-2-sean@poorly.run
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions