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authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>2026-02-02 16:07:22 +0530
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>2026-02-03 13:47:06 +0530
commita120f802e0004470fdab91e907ca43f226a73419 (patch)
tree0606ab71c6cd94739076d202f0c911f59cb3db75 /tools/perf/scripts/python/bin
parentc80311c04331f2f42446eac21d7c3528c2e3c062 (diff)
drm/i915/dp_mst: Rework pipe joiner logic in mode_valid
Refactor the logic to get the number of joined pipes. Start with a single pipe and incrementally try additional pipes only if needed. While DSC overhead is not yet computed here, this restructuring prepares the code to support that in follow-up changes. v2: - Remove fallback in case force-joiner configuration fails. (Imre) - Drop redundant MODE_OK assignment (Imre) v3: - Align with the changes in intel_dp_mode_valid(). (Imre) v4: - Set MODE_CLOCK_HIGH on DSC/rate failures aligning with SST case. (Imre) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260202103731.357416-9-ankit.k.nautiyal@intel.com
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