diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-06-12 20:36:53 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-06-19 00:23:58 +0300 |
| commit | 8984b402e02ffe8792f6debe07af55e668f4a617 (patch) | |
| tree | 0388bbad7627207760dce17b20190e8a7127b7ac /tools/perf/scripts/python/bin | |
| parent | 67d77d9472c668577dd156c22b649f64957b2c63 (diff) | |
drm/i915/cdclk: Use the TGL+ CD2x pipe select bits also on ICL
Turns out both CDCLK_CTL pipe select 0b110 (what Bspec lists for
pipe C on ICL) and 0b100 (what BSpec lists for pipe C on TGL+)
actually select pipe C on ICL. So we can get rid of the weird
ICL special case and just use the simpler TGL+ definition of
the pipe select bits.
This was reverse engineered with a hacked up intel_display_poller.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260612173653.7830-7-ville.syrjala@linux.intel.com
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions
