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| author | Sudip Mukherjee <sudip.mukherjee@sifive.com> | 2026-08-03 05:40:35 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-04 13:46:53 +0100 |
| commit | 607687a869e60333d7a6cc3621c406b6e9dc2af8 (patch) | |
| tree | da60c4ab096e02fb33ae4946b01a2f0eafdd2fef /tools/perf/scripts/python/bin | |
| parent | c87b4ba09702762ea69187561bd4d76ae602f8bd (diff) | |
spi: dw: update SPI_CTRLR0 register
If the SPI transfer is being done in enhanced mode then SPI_CTRLR0
register needs to be updated to mention the instruction length, address
length, address and instruction transfer format, wait cycles. And, we
also need to enable clock stretching.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
Co-developed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://patch.msgid.link/20260803124044.156998-3-changhuang.liang@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions