diff options
| author | Riana Tauro <riana.tauro@intel.com> | 2026-07-17 19:46:53 +0530 |
|---|---|---|
| committer | Riana Tauro <riana.tauro@intel.com> | 2026-07-20 10:13:11 +0530 |
| commit | 573f9e7ed1a97daf7db9c134fa49cad9b7f9c142 (patch) | |
| tree | 71f6164597820995dfeb67b219067f305b902f47 /tools/perf/scripts/python/bin | |
| parent | 116932705096281f402ccf779036a814ed89bf56 (diff) | |
drm/xe/xe_ras: Handle uncorrectable SoC Internal errors
Some critical errors such as CSC firmware and Punit are reported under SoC
internal errors and require special handling.
CSC errors are classified into hardware errors and firmware errors.
Hardware errors can be recovered using a SBR (Secondary Bus Reset) whereas
firmware errors are critical and require a firmware flash. On such errors,
device is wedged and runtime survivability mode will be enabled to notify
userspace that a firmware flash is required.
PUNIT uncorrectable errors can only be recovered through a cold reset.
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Link: https://patch.msgid.link/20260717141650.2487761-7-riana.tauro@intel.com
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions
