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| author | Roman Li <Roman.Li@amd.com> | 2026-04-13 17:32:55 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-04-17 15:41:15 -0400 |
| commit | 35e86e6a54e82e3624e9abdad61c8d4b0f764396 (patch) | |
| tree | fe315e04230bf082b90dbf4baeb83882e2d43c75 /tools/perf/scripts/python/bin | |
| parent | 4aebe73f44bb57ccc8bcdba15a2d56ebfe452d4d (diff) | |
drm/amd/display: bypass post csc for additional color spaces in dcn42
[Why]
This aligns dcn42 with:
"drm/amd/display: bypass post csc for additional color spaces in dal"
[How]
Apply the same post csc bypass logic to dcn42 dpp using the
helper function.
Signed-off-by: Roman Li <roman.li@amd.com>
Acked-by: Chenyu Chen <chen-yu.chen@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions