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authorVincent Jardin <vjardin@free.fr>2026-07-30 19:35:36 +0200
committerJakub Kicinski <kuba@kernel.org>2026-08-05 19:00:32 -0700
commit24e4aff8983fe663a85b5b157476f87ae0819e2c (patch)
tree652b611e40144392fba4a576e298c59f472e6957 /tools/perf/scripts/python/bin
parentd4b0ad9a81746d8415ca57197b2344b0b8b7ee08 (diff)
dpll: zl3073x: recognize the ZL30643 chip ID (0x0E3B)
The Microchip ZL30643 is a 3-channel ZL3064x line-card part that is register compatible with the ZL30733. Only the runtime chip-ID table needs the 0x0E3B entry so the probe resolves the channel count (3) and flags. The ZL3073X_FLAG_REF_PHASE_COMP_32 flag applies unchanged: the ref_phase path dpll_meas_ctrl::en -> ref_phase_0P/0N -> ref_phase_offset_compensation -> ref_phase_err_read_rqst is identical between ZL3064x and ZL3073x. No new device flag is needed. Test: once register, for instance, we get: devlink dev param set spi/spi0.0 name clock_id value 3733 cmode driverinit devlink dev reload spi/spi0.0 devlink dev param set spi/spi2.1 name clock_id value 3643 cmode driverinit devlink dev reload spi/spi2.1 dpll device show | grep clock-id clock-id: 3733 clock-id: 3733 clock-id: 3733 clock-id: 3643 clock-id: 3643 clock-id: 3643 Signed-off-by: Vincent Jardin <vjardin@free.fr> Link: https://patch.msgid.link/20260730-for-upstream-zl30643-v2-2-0ea0bbd03755@free.fr Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
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