arm64: dts: imx8mm: Explicitly set DSI_PHY_REF clock as a child of CLK_24M

Since commit a0deedcc0cf0 ("arm64: dts: imx8mm: Slow default video_pll1
clock rate") and commit 5fe6ec93f10b0 ("clk: imx8mm: Let
IMX8MM_CLK_LCDIF_PIXEL set parent rate") VIDEO_PLL1 is dynamically
programmed by CLK_LCDIF_PIXEL.

On imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso this results in a
VIDEO_PLL1 frequency of 68.2 MHz and DSI_PHY_REF of 17.05MHz (1/4).
Instead use the 24 MHz clock as parent for DSI PHY reference clock.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

0 files changed, 0 insertions, 0 deletions