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authorInochi Amaoto <inochiama@gmail.com>2026-07-13 09:02:54 +0800
committerAnup Patel <anup@brainfault.org>2026-07-29 17:57:28 +0530
commit1c05a6b7ebb2a7dc09cf06dba554eb32de7c5a04 (patch)
treefb63dea897ac36f009d36604ec16463fbd594c93 /tools/perf/scripts/python/bin
parentf5098b6bae761e346ebcd9da7f95622c04733cff (diff)
RISC-V: KVM: Add support for Svadu FWFT features
Hardware updating of PTE A/D bits is controlled through ADUE bit in henvcfg Expose the feature only if both Svadu and Svade are supported for VS-mode. Allow the VMM to enable/disable this feature by change the ISA extension state in the guest. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-2-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
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