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| author | Shubham Patil <shubhamsanjay.patil@amd.com> | 2026-07-20 13:05:09 +0530 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2026-07-31 09:28:14 +0200 |
| commit | dce830367d5f8b56520993a5f121cfd35773cabc (patch) | |
| tree | 1036ab506c4e5bff0c0ab3e7eac4f2d2ff405864 /tools/perf/scripts/python/bin/task-analyzer-record | |
| parent | a733069a1943f30922b90bde5eef3cb25b010f8b (diff) | |
dt-bindings: i3c: dw: Document missing optional core reset
The DesignWare I3C master IP supports a core reset input, but the
binding is missing the corresponding reset description.
Document the optional reset property. Keep it optional because the
reset line is integration-specific.
Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://patch.msgid.link/20260720073510.1869623-2-shubhamsanjay.patil@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/task-analyzer-record')
0 files changed, 0 insertions, 0 deletions