drm/xe/xe3p_lpg: Program TR_PTA_MODE

Up until Xe3p_LPG, the PTA_MODE register controlled cacheability of
accesses to the page tables for both PPGTT and TRTT.  Starting with
Xe3p_LPG, PTA_MODE is now only responsible for the PPGTT accesses, and a
separate register, TR_PTA_MODE is used to control the TRTT accesses. The
currently recommeded value for TR_PTA_MODE differs from PTA_MODE on
Xe3p_LPG.  Track and program this value separately in the driver.

Note that even though the Xe3p_LP[G/M] IPs didn't add support for this
new TR_PTA_MODE register until b-stepping, it's safe us to ignore that
detail code-wise.  Writes of the unrecognized registers on a-step
hardware will be silently ignored, and the reads on a-step will come
back as 0x0 which happens to be the value we'd be trying to program on
these IP versions anyway (for both graphics and media).

The new TRTT-specific register also does not exist on Xe3p_XPC
platforms.

v2:
 - Split gt_tr_pta_entry() out from gt_pta_entry().  (Gustavo)
 - Fix copy/paste mistake that caused us to write the PPGTT value to the
   TRTT register in the MCR path.  (Sashiko)

Bspec: 79814, 71582
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260716-tr_pta_mode-v2-1-e4cd50da1c94@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

0 files changed, 0 insertions, 0 deletions