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| author | Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> | 2026-06-16 21:51:47 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-06-17 18:07:56 +0530 |
| commit | eda862176c4e8edd4beebac1b8df4726fcc6719e (patch) | |
| tree | 577555fa78e0e5dd6ce132f4567e1210f9cf8390 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | d75ea53314db7a8265e5235031b487766779d73c (diff) | |
drm/i915/display: Store DC3CO eligibility in PSR state
Store DC3CO eligibility in intel_dp->psr during
intel_psr_post_plane_update() so PSR configuration
can take DC3CO into account.
This will be used to control PSR2 parameters such as idle frames.
Changes in v2:
- Use intel_display_power_dc3co_allowed(display) instead
of intel_dc3co_allowed(state)
Changes in v3:
- Update psr.dc3co_eligible before
intel_psr_enable_locked() call (sashiko)
Changes in v4:
- rename eligible to allowed (Jani Nikula)
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260616162154.2630995-10-dibin.moolakadan.subrahmanian@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions