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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2026-05-04 21:24:00 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-06-02 21:41:11 +0200 |
| commit | d1ad644e572c0647ad8428439eafea0aacfccf9e (patch) | |
| tree | b8a261f6f3eaf003de766f2da850987d70b82b47 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 9f5670802df085ad343146561e69bac43e9905d2 (diff) | |
drm/rockchip: vop2: Wait for layer cfg done before switching LAYERSEL_REGDONE_SEL
LAYERSEL_REGDONE_SEL mask of RK3568_OVL_CTRL register controls which
Video Port (VP) vsync latches the shared RK3568_OVL_{LAYER|PORT}_SEL
shadow registers into the active configuration.
rk3568_vop2_setup_layer_mixer() overwrites LAYERSEL_REGDONE_SEL to the
current VP ID before waiting for the previous VP layer configuration to
take effect. As a consequence, the previous VP vsync can no longer
trigger the latch, so the wait polls a value that might never appear.
Move the layer cfg done wait before the RK3568_OVL_CTRL write so the
previous VP vsync can still commit the pending configuration.
Fixes: 3e89a8c68354 ("drm/rockchip: vop2: Fix the update of LAYER/PORT select registers when there are multi display output on rk3588/rk3568")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20260504-vop2-layer-cfg-tmout-v1-2-730226a7331e@collabora.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions