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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-03-19 14:15:15 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-26 20:04:28 +0100 |
| commit | 494feecd60e876a4310cdda279d918e91f930091 (patch) | |
| tree | 87eeec427c34f5916d3cd7f8c533f619c718cbd0 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 9efe63b74e9c30777db9815dc5d38d667576ac6f (diff) | |
pinctrl: renesas: rzt2h: Add pin configuration support
Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H SoC
allows configuring several electrical characteristics through the DRCTLm
(I/O Buffer Function Switching) registers. These registers control bias
configuration, Schmitt trigger input, output slew rate, and drive
strength.
Implement pinconf_ops to allow reading and updating these properties
through the generic pin configuration framework. The implementation
supports bias-disable, bias-pull-up, bias-pull-down,
input-schmitt-enable, slew-rate, and drive-strength-microamp.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260319141515.2053556-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions