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| author | Mark Brown <broonie@kernel.org> | 2026-07-31 21:29:24 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-07-31 21:29:24 +0100 |
| commit | 36bd2782549c867f07040e17d73b39c75fbaab7a (patch) | |
| tree | 765bd2e3ce73585917da7160ad61213355fb448b /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 26bbeaa8b3b9a4c2b6aa44b1a726b0b4e828d349 (diff) | |
| parent | 78b16af159ae6d1f5506697c1f08d8172afdc037 (diff) | |
spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller
Chi-Wen Weng <cwweng.linux@gmail.com> says:
Add devicetree binding and SPI controller driver support for the Quad SPI
controller found in Nuvoton MA35D1 SoCs.
The controller provides two native chip selects and supports standard SPI
and spi-mem operations using single, dual and quad bus widths.
This initial implementation uses 8-bit PIO transfers and supports
per-operation clock configuration, clock and reset handling, and direct
execution of SPI memory operations. DMA and active-high chip select support
are intentionally left out of the initial driver.
Link: https://patch.msgid.link/20260731023818.1626075-1-cwweng.linux@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
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