diff options
| author | Alejandro Lucero <alucerop@amd.com> | 2026-02-28 17:36:02 +0000 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-03-16 16:32:05 -0700 |
| commit | 29f0724c4592a5ab9076e1ff6e4e39f0de60cc9e (patch) | |
| tree | f07b8ee9a94f242909e6740aefdcfec5da1a5ee0 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 09d065d256b1d5965fe6512cfd1c23ef44d2efc9 (diff) | |
cxl/region: Factor out interleave ways setup
Region creation based on Type3 devices can be triggered from user space
allowing memory combination through interleaving.
In preparation for kernel driven region creation, that is Type2 drivers
triggering region creation backed with its advertised CXL memory, factor
out a common helper from the user-sysfs region setup for interleave ways.
Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
Tested-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260228173603.1125109-3-alejandro.lucero-palau@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions