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| author | Dan Williams <dan.j.williams@intel.com> | 2026-03-22 19:53:37 +0000 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-03-27 10:19:51 -0700 |
| commit | edfcf1e21e79ddd6990a1330597c2eb072330832 (patch) | |
| tree | 22df623e7e15dd7b938640674f31a53b0af3d4b0 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 7b4bcaadfe00e2447c84378291e854ea87a2a41c (diff) | |
dax/hmem: Gate Soft Reserved deferral on DEV_DAX_CXL
Replace IS_ENABLED(CONFIG_CXL_REGION) with IS_ENABLED(CONFIG_DEV_DAX_CXL)
so that HMEM only defers Soft Reserved ranges when CXL DAX support is
enabled. This makes the coordination between HMEM and the CXL stack more
precise and prevents deferral in unrelated CXL configurations.
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20260322195343.206900-5-Smita.KoralahalliChannabasappa@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions