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| author | Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> | 2025-04-11 19:05:37 +0200 |
|---|---|---|
| committer | Hans Verkuil <hverkuil@xs4all.nl> | 2025-04-23 10:55:53 +0200 |
| commit | ed472263fcc48f72e32cb494061bf8b8c333891a (patch) | |
| tree | 8dd9597ca057e41ff414b33b3707e16fa598f6f4 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 15cef2dc7d688d5fc4919aa3c5c272931a8cd087 (diff) | |
media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoC
The RZ/V2H(P) SoC does not require a `system` clock for the CSI-2
interface. To accommodate this, introduce a `has_system_clk` bool flag
in the `rzg2l_csi2_info` structure and update the rzg2l_csi2_probe() to
conditionally request the clock only when needed.
This patch is in preparation for adding support for RZ/V2H(P) SoC.
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/r/20250411170624.472257-10-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions