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| author | Ravi Bangoria <ravi.bangoria@amd.com> | 2026-02-16 04:25:25 +0000 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-02-27 16:40:24 +0100 |
| commit | e267b4178134e36e83ddfe4f7f5b4b162a286148 (patch) | |
| tree | 4e75d56e53951ec3d274e6a8d5a0033e337f9ba2 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | f9d55ccf0199d1a80c2519084578f0c345dedd2f (diff) | |
perf/amd/ibs: Add new MSRs and CPUID bits definitions
IBS on upcoming microarch introduced two new control MSRs and couple of
new features. Define macros for them.
New capabilities:
o IBS_CAPS_DIS: Alternate Fetch and Op IBS disable bits
o IBS_CAPS_FETCHLAT: Fetch Latency filter
o IBS_CAPS_BIT63_FILTER: Virtual address bit 63 based filters for Fetch
and Op
o IBS_CAPS_STRMST_RMTSOCKET: Streaming store filter and indicator,
remote socket indicator
New control MSRs for above features:
o MSR_AMD64_IBSFETCHCTL2
o MSR_AMD64_IBSOPCTL2
Also do cosmetic alignment changes.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20260216042530.1546-3-ravi.bangoria@amd.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions