diff options
| author | Thomas Zimmermann <tzimmermann@suse.de> | 2020-05-15 10:32:23 +0200 |
|---|---|---|
| committer | Thomas Zimmermann <tzimmermann@suse.de> | 2020-05-19 09:41:33 +0200 |
| commit | db05f8d3dc875249a5a11737ca715584b72851e8 (patch) | |
| tree | 1368d029ea3fe4dfb02f2a5582f167f9707cfd5c /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | a6edae07fd015c1a9af98477e1274cd4d489c1cb (diff) | |
drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O
Set different fields in MISC in their rsp location in the code. This
patch also fixes a bug in the original code where the mode's SYNC flags
were never written into the MISC register.
v2:
* use u8 instead of uint8_t
* define MGAREG_MISC_CLK_SEL_MASK
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200515083233.32036-6-tzimmermann@suse.de
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions