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| author | Sascha Bischoff <Sascha.Bischoff@arm.com> | 2026-03-19 15:55:10 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2026-03-19 18:21:28 +0000 |
| commit | da8d9636be7e0761f69c3dadf747c725732312ff (patch) | |
| tree | ffccebeb6e48fad9d7fb53828889e19a26bdb0be /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 4d591252bacb2d004b7c7f5db439bfa23b552ee7 (diff) | |
KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5
Initialise the private interrupts (PPIs, only) for GICv5. This means
that a GICv5-style intid is generated (which encodes the PPI type in
the top bits) instead of the 0-based index that is used for older
GICs.
Additionally, set all of the GICv5 PPIs to use Level for the handling
mode, with the exception of the SW_PPI which uses Edge. This matches
the architecturally-defined set in the GICv5 specification (the CTIIRQ
handling mode is IMPDEF, so Level has been picked for that).
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260319154937.3619520-22-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions