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| author | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 01:33:24 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-06-16 16:09:58 +0530 |
| commit | a0c780e6ef0df928d8bfbcfb6d791b3e08cf7c7f (patch) | |
| tree | d64c9a31c5c77eb8c7ed35edc70f324a22766434 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | ccb4470c7f241f0161aacb26f37b272b659717a8 (diff) | |
drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr()
Make intel_set_transcoder_timings_lrr() take the target transcoder as an
explicit parameter instead of always using crtc_state->cpu_transcoder.
This allows the LRR timing programming sequence to be reused for other
transcoders (e.g. CMTG).
Move the intel_vrr_set_fixed_rr_timings() and intel_vrr_transcoder_enable()
calls out of intel_set_transcoder_timings_lrr() and into its only caller
intel_pipe_fastset(), so the helper now strictly programs the LRR timing
registers for the given transcoder.
No functional change intended.
v2:
- Add separate patch for renaming the cpu_transcoder variable. [Ville]
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-8-animesh.manna@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
