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authorPeter Ujfalusi <peter.ujfalusi@linux.intel.com>2026-08-05 15:27:47 +0300
committerMark Brown <broonie@kernel.org>2026-08-07 15:56:04 +0100
commit82da8df388004af4540e930ab3de2ce5787207e7 (patch)
tree4b1b7cf757c3cd3f7326be4497cf3893a99e2cb7 /tools/perf/scripts/python/bin/stackcollapse-record
parent597273563d90d03fda852a29c3a76c41a22bf6ac (diff)
ASoC: tegra210_i2s: sort the Tegra264 register default table
reg_defaults must be sorted by ascending register address, as regcache_lookup_reg() locates entries in it with bsearch(). See commit fd80df352ba1 ("regcache: Add support for sorting defaults arrays"). TEGRA264_I2S_ENABLE (0x100), TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE (0x30) and TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE (0xb0) are listed at the end of the table, after TEGRA264_I2S_TIMING (0x130), which leaves 4 of the 9 entries unreachable. regcache_reg_needs_sync() then cannot compare them against their default and reports that a sync is needed, so they are written to the device on every regcache_sync() even when they were never touched. Sort the table by register address. Fixes: b3354438d898 ("ASoC: tegra: I2S: Add Tegra264 support") Cc: stable@vger.kernel.org Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Link: https://patch.msgid.link/20260805122748.13090-3-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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