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| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-07-01 12:05:55 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-07-06 10:47:02 -0400 |
| commit | 77c0d4cfd43353e8bdebc4eab8e579518e2dbf5f (patch) | |
| tree | 31f77918f9f69b1b8565ae9eb2824c4f0c2d943e /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | d61fa5049fcfd3a9d048038acf6c0d5993baee12 (diff) | |
dt-bindings: arm: fsl: add Variscite DART-MX8M PLUS Boards
Add DT compatible strings for Variscite DART-MX8MP SoM and Variscite
development carrier Board.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions