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| author | Nava kishore Manne <nava.kishore.manne@amd.com> | 2026-06-27 21:22:27 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-07-22 20:52:34 +0530 |
| commit | 6cb22477929489a412df8d153e550e77a012e701 (patch) | |
| tree | c40b1b2b6ddad414b2213e82c74f07270b957397 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | f3506e15cf72e94f62d5f2d173e5b7008f644cde (diff) | |
phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask
The L0_TX_DIG_61 register bit 2 is a reserved read-only field.
The previous mask value 0x0f incorrectly included bit 2, causing
unintended writes to a reserved bit on every scrambler bypass
operation.
Correct the mask to (BIT(3) | GENMASK(1, 0)) to cover only the
valid scramble bypass control bits.
Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver")
Cc: stable@vger.kernel.org
Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/20260627155229.2791113-2-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions