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| author | Alexander Chechik <alexander.chechik@amd.com> | 2026-03-09 13:15:24 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-03-23 14:14:46 -0400 |
| commit | 6c006fac2c17797510691c1848320a1659ff58b4 (patch) | |
| tree | 19f07eb790a5107d29274a1dd32fd1713a4547b8 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | deab056486f4e9945d403ea0ef812a593b7f438e (diff) | |
drm/amd/display: Fix DCN42 memory clock table using MemClk instead of UClk
[Why]
DCN42 was using UClk values instead of MemClk from MemPstateTable, causing
DML to see half the actual DRAM bandwidth on DDR5 systems and reject high
refresh rate modes.
[How]
Change dcn42_init_clocks() to use MemPstateTable[i].MemClk instead of
MemPstateTable[i].UClk for memclk_mhz initialization.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alexander Chechik <alexander.chechik@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions