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authorMatt Roper <matthew.d.roper@intel.com>2026-02-05 13:41:40 -0800
committerMatt Roper <matthew.d.roper@intel.com>2026-02-06 09:49:20 -0800
commit6acf3d3ed6c1f0febdd046578ea9cafcd47912f4 (patch)
tree77bfc19d1f6292923debf109d90ad93f32033fb8 /tools/perf/scripts/python/bin/stackcollapse-record
parent91be6115e4677ad69bf8186988972b319d32ae61 (diff)
drm/xe: Move number of XeCore fuse registers to graphics descriptor
The number of registers used to express the XeCore mask has some "special cases" that don't always get inherited by later IP versions so it's cleaner and simpler to record the numbers in the IP descriptor rather than adding extra conditions to the standalone get_num_dss_regs() function. Note that a minor change here is that we now always treat the number of registers as 0 for the media GT. Technically a copy of these fuse registers does exist in the media GT as well (at the usual 0x380000+$offset location), but the value of those is always supposed to read back as 0 because media GTs never have any XeCores or EUs. v2: - Add a kunit assertion to catch descriptors that forget to initialize either count. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20260205214139.48515-3-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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