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authorLuke Wang <ziniu.wang_1@nxp.com>2026-02-03 19:23:10 +0800
committerFrank Li <Frank.Li@nxp.com>2026-02-24 18:09:15 -0500
commit5ab0c76df2403137a6d0fb27a55e03cedf47f44c (patch)
tree3a0771e70deb466b6010b4816480d2b785d11b85 /tools/perf/scripts/python/bin/stackcollapse-record
parent12f56ee0ad2b7512808e06a804290bc7720530b1 (diff)
arm64: dts: imx91-11x11-evk: change usdhc tuning step for eMMC and SD
During system resume, the following errors occurred: [ 430.638625] mmc1: error -84 writing Cache Enable bit [ 430.643618] mmc1: error -84 doing runtime resume For eMMC and SD, there are two tuning pass windows and the gap between those two windows may only have one cell. If tuning step > 1, the gap may just be skipped and host assumes those two windows as a continuous windows. This will cause a wrong delay cell near the gap to be selected. Set the tuning step to 1 to avoid selecting the wrong delay cell. For SDIO, the gap is sufficiently large, so the default tuning step does not cause this issue. Fixes: 6772c4cffd87 ("arm64: dts: freescale: add i.MX91 11x11 EVK basic support") Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
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