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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-02-04 08:02:47 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-02-05 08:06:39 +0530 |
| commit | 58bb61161ee121b09bd61ad26ed424c4db5c03c2 (patch) | |
| tree | 9332396cee09e70f672fa914ab430300ec4fecc1 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 05cffc0749388d5979a75039f3715b17092c3f40 (diff) | |
drm/i915/ltphy: Return true for TBT scenario during lt_phy_state compare
TBT PHY is enablement/disablement is handled by its own TBT module.
We do not play a big part in it's state management, that being take care
by it's own TBT modeule.
The PHY/PLL TypeC mode (TBT, DP-alt) can change after the PLL state was
computed for a modeset, so the state verification after the modeset
sequence would indicate a mismatch in case the mode changed from DP-alt
to TBT, or from TBT to DP-alt mode. To avoid such a mismatch error the
verification is skipped if the mode for either the read-out or the
computed state is TBT (where that TBT PLL state doesn't reflect anyway
the PLL's actual HW state).
Simply return true when we are in tbt mode.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260204023247.1560196-1-suraj.kandpal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
