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| author | Joakim Zhang <joakim.zhang@cixtech.com> | 2026-07-23 17:08:05 +0800 |
|---|---|---|
| committer | Brian Masney <bmasney@redhat.com> | 2026-07-28 11:25:29 -0400 |
| commit | 48ceae43be9f3537eee179bcc53266eadbc40bcc (patch) | |
| tree | 0c75a3692a8765f647a40aac2a207bef2d2c6c38 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 3948a36be42b67f43f1d3f113dad4c8b347efb9b (diff) | |
dt-bindings: soc: cix: add sky1 audss cru controller
The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU)
groups clock muxing, gating and block-level software reset control
in a single register block.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions