diff options
| author | Arun R Murthy <arun.r.murthy@intel.com> | 2026-02-16 10:29:39 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-02-24 08:41:59 +0530 |
| commit | 122439234f6ae2583a3701d7619f9a8242748547 (patch) | |
| tree | 37815d57ba8b65442ca392c1d1e62545fa7b09ca /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 008304c9ae75c772d3460040de56e12112cdf5e6 (diff) | |
drm/i915/cx0_phy_regs: Include SoC and OS turnaround time
The port refclk enable timeout and the soc ready timeout value mentioned
in the spec is the PHY timings and doesn't include the turnaround time
from the SoC or OS. So add an overhead timeout value on top of the
recommended timeouts from the PHY spec.
The overhead value is based on the stress test results with multiple
available panels.
Reported-by: Cole Leavitt <cole@unwrap.rs>
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14713
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260216-timeout-v3-1-055522c22560@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions