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authorPuranam V G Tejaswi <puranam.tejaswi@oss.qualcomm.com>2026-07-18 02:11:30 +0530
committerRob Clark <robin.clark@oss.qualcomm.com>2026-07-18 09:02:54 -0700
commit0b69e4f4ee325ee0b50396657fd19d4d7b0a6294 (patch)
tree89c627b97ac4a7e14709f6081c18267cc03ccfae /tools/perf/scripts/python/bin/stackcollapse-record
parentcee19f08f460bc7a9b531472f25137aa8626cd51 (diff)
dt-bindings: display/msm: Document Adreno 722 GPU and GMU
Adreno 722 found in Eliza chipset belongs to the A7x Gen1 family. It is derived from A730 and shares the same IP-level configurations: HWCG registers, protected registers, GBIF CX registers and gmu_cgc_mode. Major differences include lower cache/core counts, 1MB GMEM, no Concurrent Binning & LPAC support. Some of the peripheral blocks like RSCC are from A740 that resulted in updates to RSC layout. Update the dt-binding docs to document this GPU and GMU. Signed-off-by: Puranam V G Tejaswi <puranam.tejaswi@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/740964/ Message-ID: <20260718-eliza-gpu-v2-5-64379dbebd7a@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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