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| author | Riana Tauro <riana.tauro@intel.com> | 2024-09-06 12:41:26 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-09-06 12:13:30 -0400 |
| commit | 0914c1e45d3a1a747faeebae27ba197d7ba41f94 (patch) | |
| tree | 7239f526d0d3f4656158e8bcef18cbdf2529ff42 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | c2bf07dd0bbce1f318b73b525e21fbc6d67a3a94 (diff) | |
drm/xe/xe_gt_idle: add debugfs entry for powergating info
Coarse Powergating is a power saving technique where Render and Media
can be power-gated independently irrespective of the rest of the GT.
For debug purposes, it is useful to expose the powergating information.
v2: move to debugfs
add details to commit message
add per-slice status for media
define reg bits in descending order (Matt Roper)
v3: fix return statement
fix kernel-doc
use loop for media slices
use helper function for status (Michal)
v4: add pg prefix
do not wake GT if in C6 (Badal)
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240906071126.28078-3-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions