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authorImre Deak <imre.deak@intel.com>2026-07-14 18:26:59 +0300
committerImre Deak <imre.deak@intel.com>2026-07-20 15:47:16 +0300
commit47fff2b1749e9ba5dfab7528960555cc865360b5 (patch)
treec5b66f4411886639c59f57a08592bc9274e8065b /tools/perf/scripts/python/bin/export-to-postgresql-record
parent0f0950ca8eb20053022ce956cc3cd112279dd7bb (diff)
drm/i915/dp: Disable UHBR link configs with 1/2 lanes
Disable 1 and 2 lane link configurations on UHBR tunneled links, according to DP Standard v2.1b "3.5.2.16.3 128b/132b DPRX Lane Count Conversion Failure Indication and Corrective Action". A tunnel can indicate if it's not affected by this limitation, check for that and skip disabling the unsupported lanes for a well-behaving tunnel. The Standard in the same section also describes a workaround for 2 lanes which requires assisstance from the sink, where the sink indicates at the end of the link training sequence if the link training must be retried. This mechanism also requires quirking out some sinks - based on the sink's DPCD OUI and EDID identifications - which doesn't implement this link training feedback indication properly. This patch leaves the implementation of this workaround for a follow-up, but prepares for it already by detecting the supported number of lane counts at a place where both DPCD OUI and EDID is available for the quirk detection. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260714152700.555527-6-imre.deak@intel.com
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