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authorGuodong Xu <guodong@riscstar.com>2025-12-25 14:24:20 +0800
committerConor Dooley <conor.dooley@microchip.com>2026-01-13 22:22:29 +0000
commitfff010c776f715904ba0823bb347eac00dccffa2 (patch)
tree222bd066f7e3b0218f72ee49e22293249e02ab07 /tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git
parent4297ddbf1d148a6007b91b2aec51853454253b96 (diff)
dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt
The descriptions for h, svinval, svnapot, and svpbmt extensions currently reference the "20191213 version of the privileged ISA specification". While an Unprivileged ISA document exists with that date, there is no corresponding ratified Privileged ISA specification. These extensions were ratified in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20211203. Update the descriptions to reference the correct specification version. RISC-V International hosts a website [1] for ratified specifications. Following the "Ratified ISA Specifications", historical versions of Volume II Privileged ISA can be found. Link: https://riscv.org/specifications/ratified/ [1] Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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