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| author | Aksh Garg <a-garg7@ti.com> | 2026-01-30 17:25:16 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-02-03 17:10:15 -0600 |
| commit | e3c3a5d25dc090c237ec768fdded96e9184fe2ae (patch) | |
| tree | 3a58784b7a11c9ff8ac00c0c5e9936beeeb83251 /tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git | |
| parent | 72cb5ed2a5c6d87f71a409347f7d3b228fee6bee (diff) | |
PCI: dwc: ep: Add comment explaining controller level PTM access in multi PF setup
PCIe r6.0, section 7.9.15 requires PTM capability in exactly one
function to control all PTM-capable functions. This makes PTM registers
controller level rather than per-function.
Add a comment explaining why PTM capability registers are accessed
using the standard DBI accessors instead of func_no indexed
per-function accessors.
Suggested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Aksh Garg <a-garg7@ti.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://patch.msgid.link/20260130115516.515082-4-a-garg7@ti.com
Diffstat (limited to 'tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions