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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-01-14 09:17:46 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-01-15 10:04:27 +0100 |
| commit | d345b6bb886004ac1018da0348b5da7d9906071b (patch) | |
| tree | 5b93f89a1036f89311cfc378b74dafdd0974944c /tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git | |
| parent | d2bdcde9626cbea0c44a6aaa33b440c8adf81e09 (diff) | |
perf/x86/intel: Add core PMU support for DMR
This patch enables core PMU features for Diamond Rapids (Panther Cove
microarchitecture), including Panther Cove specific counter and PEBS
constraints, a new cache events ID table, and the model-specific OMR
events extra registers table.
For detailed information about counter constraints, please refer to
section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260114011750.350569-4-dapeng1.mi@linux.intel.com
Diffstat (limited to 'tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions