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authorBaochen Qiang <baochen.qiang@oss.qualcomm.com>2026-01-12 15:36:33 +0800
committerJeff Johnson <jeff.johnson@oss.qualcomm.com>2026-01-15 17:19:41 -0800
commitb7ffeb0f62fddc5f21c6ff610d28e08247b6b9b5 (patch)
treefbbc84a2c122d7e4ec719376b05611f6e8e762ea /tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git
parent023ace9f9232d43137f346d908996a6fee4de70a (diff)
wifi: ath12k: handle REO CMD ring for QCC2072
As far as REO CMD ring is concerned, there are two differences between QCC2072 and the existing chips: For the first, the TLV header of ring descriptor for QCC2072 is 32 bits while 64 bits for existing chips. For the second, QCC2072 has different hal_reo_get_queue_stats, hal_reo_flush_cache and hal_reo_update_rx_queue structures. Take hal_reo_get_queue_stats as an example: QCC2072: struct hal_reo_get_queue_stats_qcc2072 { struct hal_reo_cmd_hdr cmd; [...] __le32 rsvd0[6]; } __packed; QCN9274/WCN7850: struct hal_reo_get_queue_stats { struct hal_reo_cmd_hdr cmd; [...] __le32 rsvd0[6]; __le32 tlv64_pad; } __packed; Note there is no tlv64_pad at the end for QCC2072, but all other former fields share the same layout. These make different ring entry size, so that parameter has to be updated with respect to existing chips. This is done in the newly introduced ath12k_hal_srng_create_config_qcc2072() function, which first creates all ring configs by utilizing ath12k_hal_srng_create_config_wcn7850() and then updates the individual field. Besides, the REO command TLV encoding also need to be corrected because of the different TLV bits. This is done by introducing a 32 bit variant for each of the existing 64 bit callback. Note the hal_reo_get_queue_stats_qcc2072 structure is introduced for the purpose of calculating ring entry size. Existing hal_reo_get_queue_stats structure gets used elsewhere even for QCC2072. This is working because the only difference is the tlv64_pad field that is located at the end and not getting used, hence can be ignored. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0-01560-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com> Link: https://patch.msgid.link/20260112-ath12k-support-qcc2072-v2-13-fc8ce1e43969@oss.qualcomm.com Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
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