diff options
| author | Baochen Qiang <baochen.qiang@oss.qualcomm.com> | 2026-01-12 15:36:22 +0800 |
|---|---|---|
| committer | Jeff Johnson <jeff.johnson@oss.qualcomm.com> | 2026-01-15 17:19:38 -0800 |
| commit | 9615a6727e9d836e60dd4c7442bc8c16f0382203 (patch) | |
| tree | e85d5f60fb0e7990e55e2f0b959b166c7fe13459 /tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git | |
| parent | 7a6b6386deb71908181adc26c6ddbe9bc6cef169 (diff) | |
wifi: ath12k: refactor REO CMD ring handling
The entry of REO CMD ring of existing chips has a 64 bit TLV header, hence
below functions take a 64 bit TLV assumption by default
ath12k_wifi7_hal_reo_init_cmd_ring()
ath12k_wifi7_hal_reo_cmd_queue_stats()
ath12k_wifi7_hal_reo_cmd_flush_cache()
ath12k_wifi7_hal_reo_cmd_update_rx_queue()
However this is not the case for QCC2072 of which the TLV is 32 bit,
meaning above functions don't work for it.
Rename/refactor above functions to prepare for QCC2072 support:
Rename the first one to ath12k_wifi7_hal_reo_init_cmd_ring_tlv64() to
better reflect what it is doing. There will be a 32 bit variant when
QCC2072 support is in place.
For the last ones, remove TLV length assumption and offload TLV encoding
work to a newly added callback _reo_cmd_enc_tlv_hdr. This way each chip
can register its own handler hence can do the work accordingly.
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3
Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260112-ath12k-support-qcc2072-v2-2-fc8ce1e43969@oss.qualcomm.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
Diffstat (limited to 'tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions
