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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-12-17 13:15:10 +0200 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-12-30 22:41:25 +0530 |
| commit | 62d4911290f9cbb16f5b6ba6782660148a656fc7 (patch) | |
| tree | d416b487522776ba76af4965f57330642fb1b2bf /tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git | |
| parent | 4b86eff47e205819eb862097493ec20e25ac8f56 (diff) | |
PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS
The RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS registers are of the R/W1C
type. According to the RZ/G3S HW Manual, Rev. 1.10, chapter 34.2.1
Register Type, R/W1C register bits are cleared to 0b by writing 1b, while
writing 0b has no effect. Therefore, there is no need to take a lock
around writes to these registers.
Drop the locking.
Along with this, add a note about the R/W1C register type to the register
offset definitions.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://patch.msgid.link/20251217111510.138848-3-claudiu.beznea.uj@bp.renesas.com
Diffstat (limited to 'tools/perf/lib/Documentation/tutorial/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions