drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

Add MIPI DSI support for the Renesas RZ/V2H(P) SoC. Compared to the
RZ/G2L family, the RZ/V2H(P) requires dedicated D-PHY PLL programming,
different clock configuration, and additional timing parameter handling.
The driver introduces lookup tables and helpers for D-PHY timings
(TCLK*, THS*, TLPX, and ULPS exit) as specified in the RZ/V2H(P) hardware
manual. ULPS exit timing depends on the LPCLK rate and is now handled
explicitly.

The implementation also adds support for 16 bpp RGB format, updates the
clock setup path to use the RZ/V2H PLL divider limits, and provides new
.dphy_init, .dphy_conf_clks, and .dphy_startup_late_init callbacks to
match the RZ/V2H sequence.

With these changes, the RZ/V2H(P) can operate the MIPI DSI interface in
compliance with its hardware specification while retaining support for
existing RZ/G2L platforms.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20251015192611.241920-8-prabhakar.mahadev-lad.rj@bp.renesas.com

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