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authorAksh Garg <a-garg7@ti.com>2026-04-02 14:25:45 +0530
committerManivannan Sadhasivam <mani@kernel.org>2026-04-04 22:55:27 +0530
commitd9cf7154deed71a4f23e81101571c79cdc77be00 (patch)
tree3c116a6762ed0d569c21ec32df7dbf429bf6f473 /tools/lib/python
parent6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f (diff)
PCI: cadence: Use cdns_pcie_read_sz() for byte or word read access
The commit 18ac51ae9df9 ("PCI: cadence: Implement capability search using PCI core APIs") assumed all the platforms using Cadence PCIe controller support byte and word register accesses. This is not true for all platforms (e.g., TI J721E SoC, which only supports dword register accesses). This causes capability searches via cdns_pcie_find_capability() to fail on such platforms. Fix this by using cdns_pcie_read_sz() for config read functions, which properly handles size-aligned accesses. Remove the now-unused byte and word read wrapper functions (cdns_pcie_readw and cdns_pcie_readb). Fixes: 18ac51ae9df9 ("PCI: cadence: Implement capability search using PCI core APIs") Signed-off-by: Aksh Garg <a-garg7@ti.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260402085545.284457-1-a-garg7@ti.com
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