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| author | Michal Simek <michal.simek@amd.com> | 2026-07-08 15:12:24 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2026-07-21 09:53:48 +0200 |
| commit | d0d3f0f8aed45c93802e79e8a0dd959d538a49fa (patch) | |
| tree | 8b3935f4dc453d7bba0f8068fd41146c982fea25 /tools/lib/python | |
| parent | 6e32cb10cf32e60cf40ad0baa37c54969f10101f (diff) | |
dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema
The ZynqMP clock controller binding shares only #clock-cells with the
Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema.
Also remove "(Optional clock)" from clock description because it is visible
from schema itself.
Also update versal-firmware example to match changes in
xlnx,zynqmp-firmware.yaml.
Suggested-by: Rob Herring <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/973a8a5441cf13622594b95dd0dd20a5f42ccece.1783516336.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions
